1. Technical Field of the Invention
The present invention relates generally to phase-locked loop circuits, and more specifically, to self-biased phase-locked loop circuits.
2. Background Information and Description of Related Art
Phase-locked loops or “PLLs” have been widely used in data communications, local area networks, microprocessors, and data storage applications to generate secondary clock signals based upon a given reference signal. Generally, PLLs are considered to be either self-biased or non self-biased. Non self-biased PLLs typically use discrete circuitry requiring no a priori relationships between the various components of the PLLs other than having common interfaces. However due to their discrete nature, devices in a non self-biased PLL can independently vary potentially causing problems with tracking.
In contrast, self-biased PLLs utilize devices whose performances are intricately linked such that when one parameter of one device varies, the PLL automatically adjusts other devices to compensate for the change. Although this provides for better tracking than that available from non self-biased PLLs, self-biased PLLs typically require additional startup circuitry not required by non self-biased PLLs to jumpstart analog circuitries in transitioning from a stable zero-current state to a correct operating point.
FIG. 1 illustrates one example of a conventional self-biased phase-locked loop 100. Conventional PLLs, such as PLL 100, generally include a phase-frequency detector (PFD) 102 for monitoring a phase difference between a reference signal 104 and a feedback signal in the form of a frequency divided output signal (VCO Clk 106) of a voltage-controlled oscillator (VCO) 126. The PFD 102 generates an UP control signal 110 and a DOWN control signal 112 to cause a charge pump 114 to respectively charge and discharge a loop filter 116. The loop control voltage 118 developed across the loop filter 116 determines the output frequency of the VCO 126. Furthermore, the UP and DOWN control signals 110, 112 driving the charge pump 114 set the proper loop filter control voltage 118 to maintain a minimal phase error between the input signals applied to the PFD 102. Additionally, the bias generator 120 generates two bias voltages, VBN 122 and VBP 124. VBN 122 controls the VCO 126 and the charge pump 114 to facilitate self-biasing of the PLL, while VBP 124 functions as the control voltage of the VCO 212.
In PLLs, such as PLL 100 that utilize controlled oscillators such as VCO 126, the frequency of the target output signal from the PLL typically depends upon the frequency of the signal output by the controlled oscillator. Operation of such controlled oscillators is typically influenced or controlled by what is referred to as a control voltage. In general, as the control voltage decreases, the output frequency of the PLL increases, and as the control voltage increases, the output frequency of the PLL decreases. In the past, self biased PLLs were jumpstarted by configuring the PLL such that the control voltage would always be pulled down to one-half of the supply voltage by e.g. startup circuitry 128. After reaching one-half the supply voltage, the PLL would be allowed to operate freely so as to acquire a lock based upon the reference signal.
Although such a configuration might work successfully for single fixed voltages, such conventional jumpstart circuitries fail across multiple operating voltages. For example, when a one-volt supply voltage is pulled to what is referred to as “half-rail” (e.g. one-half of the supply voltage or 500 mV in this case), a PLL that requires 300 mV-400 mV to turn on may function properly. However, when the same PLL is placed in a system such as a microprocessor operating at a fixed or reduced voltage level of 700 mV (or 0.7 volts), the same PLL may not function properly since the resulting half-rail voltage of 350 mV is not large enough to turn on the PLL devices. Although startup voltages could be set artificially high, doing so would result in extremely long PLL lock times.